1. Technical Field
The present invention relates in general to a method and system for data processing and in particular to an improved method and system for halting the execution of a processor. Still more particularly, the present invention relates to a method and system for halting the execution of instructions by a processor in response to an enumerated occurrence of a selected combination of internal processor states.
2. Description of the Related Art
Some state-of-the-art processors, such as the PowerPC.TM. line of processors available from IBM Microelectronics, provide a service processor known as a common on-chip processor (COP) to enable testing of the processor hardware. The COP supports a scan testing debugging methodology by providing a JTAG (IEEE Standard 1149.1) interface, a scan control, and a processor control to start, reset, and stop execution of instructions by the processor.
As will be appreciated by those skilled in the art, processor hardware can be analyzed as a number of interconnected latches and combinatorial logic circuits. While the processor is under test, the COP allows a programmer to select breakpoints at which the processor is stopped and its state (i.e., the state of each of the latches within the processor) is accessed. For example, processor control options can be selected to enable breakpoints to be set after each instruction within testing software, after a predetermined number of processor cycles have elapsed, or upon access by the processor to a particular address within memory.
Typically, the COP supports two methods for stopping execution of instructions by the processor. A hardstop automatically halts processor execution at the specified breakpoint regardless of the state of the processor. Because of on-going activities within the system in which the processor is integrated, a processor cannot continue operating subsequent to a hardstop without undergoing a reset. In contrast to a hardstop, a softstop allows certain processor functions, such as bus transfers and memory management table walks to complete before processor execution is halted. Following a softstop, processor execution can be resumed, thereby enabling a programmer to determine the effect of particular processor states at later points within the execution stream.
Although a COP provides a convenient and powerful low-level debugging tool for testing processor hardware in situ, the COP does not give a user complete freedom to specify breakpoints at which to test the processor. For example, a preferred method for tracking a problem is to set a breakpoint at the address of a particular instruction. However, because an error may not occur each time the breakpoint address is accessed, debugging the processor hardware utilizing the COP can be inefficient since the processor is halted each time the breakpoint address is accessed. Furthermore, because of the looping structure of typical software, the breakpoint address can be referenced hundreds or thousands of times before the iteration at which the processor error occurs is reached.
Consequently, it would be desirable to provide an improved method and system for halting execution of a processor in response to a predetermined iteration of a selected event. In particular, it would be desirable to provide an improved method and system which enable the execution of a processor to be halted upon a selected access to a predetermined address.